Found about 6 results
Downloads: 134
Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014
240 - 244A Novel Approach to 32-Bit Approximate Adder
Shalini Singh [6] | Ghanshyam Jangid [6]
Downloads: 118 | Weekly Hits: ⮙1 | Monthly Hits: ⮙2
Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014
127 - 131A 64 Bit Pipeline Based Decimal Adder Using a New High Speed BCD Adder
Rahul Jain [3] | Khushboo Singh [2] | Ghanshyam Jangid [6]
Downloads: 118
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 8, August 2014
757 - 759Inculcation of Simultaneous Clock Gating and Power Gating in Sequential Design
Vivek Dadheech | Ghanshyam Jangid [6]
Downloads: 113
Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014
925 - 929Area and Delay Analysis of Modulo 2n ± 1 Adder Subtractor Using Prefix Adder on Weighted One and Diminished-1
Kishore Kunal | Ghanshyam Jangid [6]
Downloads: 110
Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 8, August 2014
1731 - 1733Leakage Power Reduction in CMOS XOR Full Adder Using Power Gating With GDI Technique
Piyush Sharma [3] | Ghanshyam Jangid [6]
Downloads: 109
Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014
580 - 587Study and Analysis of Different Parameters and Power Consumption of Various Multipliers in FIR Filter using VHDL
Sushant Shekhar | Ghanshyam Jangid [6]